1. Field of the Invention
The present invention relates to a semiconductor process, and more particularly, to a gate structure and a method for fabricating the same.
2. Description of Related Art
Along with rapid progress of semiconductor technology, dimensions of semiconductor devices are reduced and the integrity thereof are promoted continuously to further advance the operating speed and performance of integrated circuits (ICs). As the demand for device integrity is raised, any changes in physical characteristics, such as electrical properties, have to be considered to avoid a great impact on the performance of the device.
Taking a metal-oxide-semiconductor (MOS) device as an example, with the continual miniaturization of the semiconductor devices, dimensions of a gate structure are also gradually reduced. Therefore, thickness of a gate dielectric layer also needs to be diminished, correspondingly. There are also more stringent demands for the quality of the gate dielectric layer, such as interface properties between the gate dielectric layer and the substrate. Generally, the gate dielectric layer is usually made of silicon oxide (SiO2). Degradation of the electrical properties, such as occurrence of leakage current, frequently occurs when reducing the thickness of the gate dielectric layer adopting silicon oxide.
In order to reduce the thickness of the gate dielectric layer and ensure the electrical performance at the same time, a conventional method is to dope the gate dielectric layer of silicon oxide with high-density N2 plasma, that is, so-called decoupled plasma nitridation (DPN), so that nitrogen-doped silicon oxide (i.e. SiON) is formed as the gate dielectric layer. The DPN-treated gate dielectric layer, however, encounters problems of relatively low nitrogen content contained in the gate dielectric layer. If the nitrogen content of the gate dielectric layer requires further enrichment, power of the N2 plasma or processing time has to be raised in the DPN process. Augmentations of the plasma power or the processing time may cause nitrogen to be distributed even close to the substrate, thereby resulting in a great impact on channel performance of the MOS device.